System and method for intergration processing of different network protocols and multimedia traffics

ABSTRACT

The present invention relates to a communication system architecture which can perform integrated processing of different network protocols and multimedia traffics. The communication system for integrated processing of different network protocols and multimedia traffics comprises a common packet; a common packet switch; a plurality of channels; a common bus; a common protocol platform; an external network protocol converter; and an internal network protocol converter. Thus, the present invention can process traffics rapidly embodied by mean of hardware, and easily perform various QoS, traffic control, and so on by designing a unified common platform with an open architecture. In addition, the present invention can be used for digital consumer devices in building networks and home networks or various digital appliances classified as Internet information appliances, and for control systems such as a home gateway, a home server, an STB, a home station and so on.

TECHNICAL FIELD

The present invention relates to communication system architectures and,more particularly, to a communication system architecture which canperform integrated processing of different network protocols andmultimedia traffics.

BACKGROUND ART

In general, gateways perform protocol conversions at the end point ofnetworks using different network protocols so that each device canunderstand data from other networks. Generally, conventional gatewayshave provided services based on a one-to-one protocol conversion.

Thus, for a number, n, of different protocol networks and a number, m,of other different protocol networks, there are two methods by whicheach network can communicate with one another. First, based on thenumber of networks that have to be connected, a plurality of gateways,each of which connects two networks, are used. Second, m networkinterfaces are established through merging gateways for one-to-oneprotocol conversion, and each interface has (m−1) compatible modules totransform data. Here, (m−1) means to exclude a network identical toitself from the number of the other side networks. The output of eachmodule within each interface is connected to all of the other sidenetworks. Accordingly, the number of compatible modules within eachinterface increases according to the number of network interfaces andthe number of networks to be converted and outputted in each interfacein order to support compatibility among various networks.

Moreover, in prior art, it was difficult to embody a multi-protocolconversion because the conversion between protocols was performed in aone-to-one way such as ADSL-Ethernet, ADSL-HomePNA, Cable-Ethernet,Cable-HomePNA, and so on. To perform the multi-protocol conversion, acircuit was designed using a plurality of chipsets embodied by theabove-mentioned methods, and protocols and datagram were converted bysoftware. In other words, datagram was stored in a memory and thedatagram stored was converted into desired datagram by means ofappropriate software.

However, with such conventional multi-protocol conversion method, it isdifficult to process high-speed mass data in real time and impossible toconvert a plurality of protocols simultaneously. In addition, anotherproblem is high costs due to lots of additional circuits to designmulti-protocol conversion circuits.

DISCLOSURE OF INVENTION

Accordingly, the present invention is directed to a new communicationsystem architecture, which can process different network protocolssimultaneously, that substantially obviates one or more problems due tolimitations and disadvantages of the related art.

An object of the present invention is to provide a communication systemarchitecture for integrated processing of different network protocolsand multimedia traffics, which can perform integrated processing on ahome network having various types of networks and traffics and rapidlyprocess mass data at the same time as performing multi-channelprocessing by allocating various kinds of packets to each channel andprocessing them on a channel-by-channel basis.

Additional advantages, objects, and features of the invention will beset forth in part in the description which follows and in part willbecome apparent to those having ordinary skill in the art uponexamination of the following or may be learned from practice of theinvention. The objectives and other advantages of the invention may berealized and attained by the structure particularly pointed out in thewritten description and claims hereof as well as the appended drawings.

To achieve the object and other advantages and in accordance with thepurpose of the invention, as embodied and broadly described herein, thepresent invention provides a communication system for integratedprocessing of different network protocols and multimedia traffics,comprising:

a common packet having a header and data to process multi-protocol;

a common packet switch for switching, bridging, and routing the commonpacket internally;

a plurality of channels for exchanging packets through dedicated linesaccording to types of packets;

a common bus for transmitting the common packet to/from the commonpacket switch;

a common protocol platform able to build free topology through anaddress translation so as to perform integrated processing of differentprotocols, different packet formats and so on;

an external network protocol converter for converting a packet receivedfrom a wide area network into a common packet; and

an internal network converter for converting a packet received from alocal area network into a common packet.

In addition, the present invention provides a method for integratedprocessing of different network protocols and multimedia traffics,comprising the steps of:

converting a packet received from a wide area network into a commonpacket on an external network protocol converter, or converting a packetreceived from a local area network into a common packet on an internalnetwork protocol converter;

switching the common packet so that they can be switched, bridged, androuted internally;

channelizing to exchange packets through dedicated lines according totypes of packets;

loading the common packet on a common bus to transmit the common packetto/from a common packet switch; and

identifying a destination address of the common packet and performing anappropriate protocol conversion on a common packet platform, the commonpacket platform being able to build free topology through an addresstranslation.

It is to be understood that both the foregoing general description andthe following detailed description of the present invention areexemplary and explanatory and are intended to provide furtherexplanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

Further objects and advantages of the invention can be more fullyunderstood from the following detailed description taken in conjunctionwith the accompanying drawings, in which:

FIG. 1 illustrates a communication system architecture designedaccording to the present invention;

FIG. 2 illustrates a process of transmitting packets from a WAN to aLAN;

FIG. 3 illustrates a process of transmitting packets from a LAN to aWAN;

FIG. 4 illustrates a process of transmitting packets from a LAN toanother LAN;

FIG. 5 is a block diagram of a chipset embodied according to the presentinvention; and

FIG. 6 is an example of various network structures embodied according tothe present invention.

<Reference>  10: WAN protocol converter (WPC)  20: common packet (CP) 30: common bus (CB)  40: common packet switch (CPS)  50: commonprotocol platform (CPP)  60: LAN protocol converter (LPC) 100: physicallayer (PHY) 110: interface 120: buffer controller 130: output buffer140: input buffer 150: buffer controller 160: traffic management 170:anything-to-CP converter 180: CP-to-anything converter 190: addresstable 200: controller 210: reassembly 220: segmentation 230: commonpacket switch (CPS) 240: common bus (CB) 250: memory controller 260: buscontroller 270: scheduler 280: QoS & priority controller 290: CP packetmemory 300: linked list buffer 310: QoS buffer 320: priority buffer 400:wide area network (WAN) 410: xDSL 420: cable modem 430: Ethernet 440:room 1 450: station 1 460: common packet (CP) 470: common packet switch(CPS) 480: twist pair (TP) 490: room 2 500: station 2 510: radiofrequency (RF) 520: room 3 530: station 3 540: peer-to-peer 550: ringnetwork 560: bus network 570: star network 580: power line communication(PLC)

BEST MODE FOR CARRYING OUT THE INVENTION

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings.

FIG. 1 is a communication system architecture designed according to thepresent invention. As shown in FIG. 1, a communication system of thepresent invention comprises a common protocol platform (hereinafterreferred to as “CPP”) block (50), a WAN protocol converter (hereinafterreferred to as “WPC”) block (10), a LAN protocol converter (hereinafterreferred to as “LPC”) block (60), a common packet (hereinafter referredto as “CP”) block (20), a common bus (hereinafter referred to as “CB”)block (30), and a common packet switch (hereinafter referred to as“CPS”) block (40).

The WPC (10) comprises a buffer part that stores temporarily externalnetwork packets received, a conversion part that converts the packetsinto a form of CP, and a loader part that loads the CP on the CB totransmit to the CPS. The WPC (10) converts datagram received from anexternal network interface such as xDSL, Cable modem, Metro Ethernet,ISDN, CDMA, and PSTN into CP (20) datagram. On the contrary, intransmitting the datagram from an internal network to an externalnetwork, the WPC (10) converts the CP (20) datagram into externalnetwork datagram as desired.

The CP (20) is datagram having a uniform length so as to performintegrated processing of various types of external and internal networkdatagrams and exchange data efficiently. All external and internalnetwork datagrams are converted into the CP (20) and processedinternally.

The CB (30) is a physical interface to transmit datagram when the CP(20) datagram is transmitted to a switching block or the switcheddatagram is transmitted to a destination.

The CPS (40) comprises a buffer part that stores temporarily commonpackets received, a header translation part where a new destinationaddress as desired is added to a header, a loader part where a headerwith the new destination address and existing data are loaded on thecommon packet, and a separate channel part based on types of trafficclasses. In the CPS (40), the CP (20) entered through the CB (30) isstored temporarily, a new destination address is added to a header ofthe CP after the destination address is determined, and, then, the CP istransmitted. The CPS (40) is divided into various channels, i.e.,separate data paths, based on types of traffic classes. The channelscomprise an Internet data channel, an audio channel, a video channel, acontrol channel, a video stream channel, a voice channel, and so on,each of which may be designed as multi-channel.

The LPC (60) comprises a buffer part where internal packets entered arestored temporarily, a conversion part where the packets are convertedinto a form of CP, and a loader part where the CP is loaded on the CB tobe transmitted to the CPS. In addition, the LPC (60) converts datagramreceived from an internal network interface such as WLAN, HPNA, PLC,LonWorks, USB, Bluetooth, IEEE1394, and so on into CP (20) datagram. Onthe other hand, in transmitting the datagram from an external network toan internal network, the LPC (60) converts the CP (20) datagram into aninternal network datagram as desired.

The CPP (50) comprises various network protocols used for integratedprocessing of various types of networks. For example, there are an L2/L3switching and routing protocol, protocols for conversion betweenprotocols, and protocols necessary for integrated processing such as amethod of address conversion, MIB for integrated management, a method oftraffic priority, a scheduling method, security, quality of service(hereinafter referred to as “QoS”), and multicast.

FIG. 2 illustrates a process of transmitting packets from a WAN to aLAN. As shown in FIG. 2, when data is transmitted from a WAN to a homenetwork, packet data received from, for example, xDSL or Cable Modemusing an existing protocol changes into the CP (20) via the WPC. The CP(20) has a common packet structure compatible with all packets and istransmitted into the CPS block (40) through the CB (30). The CB (30)serves as a physical interface for transmitting the CP (20) to/from theCPS block (40). The CPS block (40) adds a destination address of thedata identified from the CPP block (50) to a header of the CP (20).Here, the CPP (50) performs an appropriate protocol conversion. Then,the CP (20) is loaded on the CB (30) to be transmitted to the LPC (60).The LPC (60) identifies the header of the CP (20) received, converts theCP (20) into internal network datagram corresponding to the destinationaddress, and transmits the datagram to the internal network.

FIG. 3 illustrates a process of transmitting packets from a LAN to aWAN. As shown in FIG. 3, when data is transmitted from a home network toan external network, packet data received from existing networks such asHPNA, Ethernet, and Bluetooth is converted into the CP (20) in the LPC(60), an internal network protocol converter. Then, the CP (20) istransmitted to the CPS block (40) through the CB (30). The CB (30)serves as a physical interface for transmitting the common packetto/from the CPS block (40). The CPS block (40) adds a destinationaddress of the data identified from the CPP block (50) to a header ofthe CP (20). Here, the CPP (50) performs an appropriate protocolconversion. Then, the CP (20) is loaded on the CB (30) to be transmittedto the WPC (10). The WPC (10) selects a WAN port corresponding to theheader of the CP, converts the CP (20) into appropriate external networkdatagram, and transmits the datagram to the WAN port selected.

FIG. 4 illustrates a process of transmitting packets from a LAN toanother LAN. As shown in FIG. 4, if there are an internal network 1 as aLonWorks network and an internal network 2 as an IEEE1394 network, indata communications between the internal network 1 and the internalnetwork 2, data received from the internal network 1 is inputted intothe LPC1, an internal network protocol converter, and converted into theCP (20). Then, the CP (20) is transmitted to the CPS block (40) throughthe CB (30). The CB (30) serves as a physical interface for transmittingthe CP (20) to/from the CPS block (40). The CPS block (40) adds adestination address of the data identified from the CPP block (50) to aheader of the CP (20). Here, the CPP (50) performs an appropriateprotocol conversion. Then, the CP (20) is loaded on the CB (30) to betransmitted to the LPC2. The LPC2 selects an internal network portcorresponding to the destination address after identifying thedestination address added to the header of the CP, and converts the CPinto appropriate internal network datagram to transmit it to theinternal network port.

FIG. 5 is a block diagram of a chipset embodied according to the presentinvention. For example, when with this chipset a home IEEE1394 equipmentsupporting IP over IEEE1394 communicates with a PC connected to aninternal or an external IP network or IEEE1394 equipment supportingother IP over IEEE1394, an interface (110) (included into WPC or PLCblock) serves as a transmission path to an external PHY (physical layer)(100) chip and, on occasion, not just as a physical layer. In addition,the interface (110) converts serial data into parallel data, andtransmits the parallel data to an input buffer (140).

The input buffer (140) (included into WPC block or LPC block) has a formof a typical ring buffer. A buffer controller (120) controls the inputbuffer (140) or an output buffer (130). In addition, the buffercontroller (120) plays a role in managing pointers and transmitting tonext block or discarding the data stored in buffer to work largely as aring buffer.

A traffic management block (160) (included into CPP block) performs aninternal traffic management algorithm, and transmits control signals tothe buffer controller (120) so as to transmit or discard data stored inthe buffer controller (120).

An anything-to-CP converter (170) (included into WPC block or LPC block)performs a packet classification algorithm, identifies a type andcharacteristics of the data entered, and creates a CP header containingswitching information, QoS class, security, and so on. Theanything-to-CP converter adds the CP header to the packet entered bymeans of encapsulation and, then, the packet with the CP header istransmitted to a segmentation block (220). Here, a separate addresstable (190) manages information such as a source address and adestination address extracted from the packet entered.

The segmentation block (220) (included into CP block) splits a payloadpart of the entered packet on a basis of a fixed size of 256 bytesincluding the header, and loads them on the CB (240). Here, segmentationinformation (i.e., a sequence number) is entered into the CP header. Inaddition, the segmentation block comprises a controller to communicatewith a common bus controller (260).

The common bus (240) provides a transmission path to send packets from aplurality of nodes to a switching block, and, in reverse direction, fromthe switching block to the corresponding output node. Here, the commonbus performs an arbitration function so that at a particular moment onlyone node can use the bus through communications between control blocksin the segmentation block (220) and a reassembly block (210) and the buscontroller (260). The packet received through the common bus (240) istransmitted to the switching block and again to the reassembly block(210) through the common bus (240).

The packet of 256 bytes entered into CPS block is stored in an externalSRAM. Here, two external SRAMs are used. One is used to store the CPpacket, and the other serves as a linked list (300) of CP packet memory,a QoS buffer (310), and a priority buffer (320).

In the QoS and priority blocks, the QoS block (310) in the CPS performsa corresponding QoS algorithm; and determines a class of the packetentered to store it in a class buffer (FIFO) in regular sequence. Then,the packet is rearranged in the priority buffer (FIFO) (310) after thepriority of the packet stored in the class buffer is determined.Subsequently, a scheduler (270) transmits the packet to the reassemblyblock (210) through the common bus (240) according to the prioritysequence.

The reassembly block (210) rearranges the packet received in regularsequence and transmits it to a CP-to-anything converter (180).

Finally, the CP-to-anything converter (180) removes the CP header fromthe packet received, and transmits the packet to the PHY (100) of alower node through the output buffer (130) and the interface (110).

FIG. 6 is an example of various network structures embodied according tothe present invention. It shows a structure of networks between stationsand between stations and digital appliances. Here, the station means ahome station system such as a home gateway, a home server and a set-topbox, which is established using a chip of the present invention.

Referring to FIG. 6, room 1 (440), room 2 (490), and room 3 (520) may beincluded into one network like rooms connected to one another in a home,and may be an independent network, respectively, like first, second, andthird floor in a building. In addition, station 1 (450), station 2(500), and station 3 (530) may be included in digital appliances asterminals.

If the room 1 (440), the room 2 (490), and the room 3 (520) constituteone network, the station 1 (450) can perform integrated management forT1˜T6 terminals, which are connected to the station 2 (500) of the room2 (490), and communicate with them by being connected with station 2(500) by means of a TP (twisted pair) (480). In other words, T11 and T12terminals connected directly to the station 1 of the room 1 can directlycommunicate with the T1˜T6 terminals and T7˜T10 terminals which areconnected to the station 3 (530) of the room 3 (520). This structuremakes it possible to perform data communication using any transmissionmedia and protocol, for example, TP (590), PLC (580) and RF (510).Moreover, all of the T1˜T12 terminals can communicate with one anothersimultaneously. The station 1 (450) can communicate with a plurality ofWANs (400) simultaneously through WPC1, WPC2 and WPC3 without connectingthe station 2 (500) and the station 3 (530) to the WAN (400).

If the room 1, the room 2, and the room 3 are independent networks,respectively, the station 1 (450), the station 2 (500), and the station3 (530) can communicate with one another, and also each station cancommunicate with the WAN (400) through the WPC. In addition, eachstation can accept all the network configurations such as a ring network(550), a star network (570), a bus network (560), and so on.

If station functions are included into terminals, the present inventioncan be used to integrate each terminal like the station, and make itpossible to perform peer-to-peer communications (540) between digitalappliances by designing the functions of the present invention invarious digital appliances (i.e., included in terminals such as theT1˜T12).

INDUSTRIAL APPLICABILITY

Thus, a system and method for integrated processing of different networkprotocols and multimedia traffics according to the present invention canprocess traffics rapidly embodied by mean of hardware, and easilyperform various QoS, traffic control, and so on by designing a unifiedcommon platform with an open architecture. In addition, the presentinvention can be used for digital consumer devices in building networksand home networks or various digital appliances classified as Internetinformation appliances, and for control systems such as a home gateway,a home server, an STB, a home station and so on, which control variousdigital appliances and appliances for building automation and homeautomation connected to networks.

1. A method for integrated processing of different network protocols andmultimedia traffics, comprising the steps of: (a) converting a packetreceived from a wide area network into a common packet on an externalnetwork protocol converter, or converting a packet received from a localarea network into a common packet on an internal network protocolconverter; (b) switching said common packet so that said common packetcan be switched, bridged, and routed internally; (c) channelizing toexchange said common packet through dedicated lines according to typesof packets; (d) loading said common packet on a common bus to transmitsaid common packet to/from a common packet switch; and (e) identifying adestination address of data and performing an appropriate protocolconversion on a common packet platform, said common packet platformbeing able to build free topology through an address translation.
 2. Themethod of claim 1, wherein said step (a) comprises the steps of: storingtemporarily an external or internal network packet entered in a buffer;converting said packet into a common packet format; and loading saidcommon packet on said common bus to transmit said common packet to saidcommon packet switch.
 3. The method of claim 1, wherein said step (b)comprises the steps of: storing temporarily said common packet enteredin a buffer; adding a new destination address as desired to a header;and loading said header on said common packet to transmit said header tothe new destination.
 4. The method of claim 1, wherein said steps (a),(b), (d) and (e) are modularized so that each of them can be operatedindependently and they can interwork with one another.
 5. The method ofclaim 1, wherein said steps (a), (b), (d) and (e) constitute a pluralityof block combinations according to functions.
 6. The method of claim 1,wherein said steps (a), (b), (d) and (e) are integrated on a chip sothat they can work as a single chip.
 7. The method of claim 1, wherein,in order to support a plug and play function, said steps (a), (b), (d)and (e) are designed as an open architecture and external networks orinternal networks interwork with said common packet platform.
 8. Themethod of claim 1, wherein, in addition to different network protocolconversions through said step (a), an overlay function toward commonpacket is supported.
 9. A system for integrated processing of differentnetwork protocols and multimedia traffics, comprising: a common packethaving a header and data to process multi-protocol; a common packetswitch for switching, bridging, and routing said common packetinternally; a plurality of channels for exchanging said common packetthrough dedicated lines according to types of packets; a common bus fortransmitting said common packet to/from said common packet switch; acommon protocol platform able to build free topology through an addresstranslation so as to perform integrated processing of differentprotocols, different packet formats, and so on; an external networkprotocol converter for converting a packet received from a wide areanetwork into a common packet; and an internal network protocol converterfor converting a packet received from a local area network into a commonpacket.
 10. The system of claim 9, wherein said common packet switchcomprises: a buffer part storing temporarily said common packet entered;a separate channel part based on types of traffic classes; a headerconversion part where a new destination address as desired is added to aheader; and a loader part loading existing data and said header withsaid new destination address on said common packet.
 11. The system ofclaim 9, wherein said external network protocol converter comprises: abuffer part storing temporarily an external network packet entered; aconversion part converting said external network packet into said commonpacket; and a loader part loading said common packet on said common busto transmit said common packet to said common packet switch.
 12. Thesystem of claim 9, wherein said internal network protocol convertercomprises: a buffer part storing temporarily an internal network packetentered; a conversion part converting said internal network packet intosaid common packet; and a loader part loading said common packet on saidcommon bus to transmit said common packet to said common packet switch.13. The system of claim 9, wherein said common packet, said common bus,said common packet switch, said common packet platform, said externalnetwork protocol converter, and said internal network protocol converterare modularized so that each of them can be operated independently andthey can interwork with one another.
 14. The system of claim 9, whereinsaid common packet, said common bus, said common packet switch, saidcommon packet platform, said external network protocol converter, andsaid internal network protocol converter constitute a plurality of blockcombinations according to functions.
 15. The system of claim 9, whereinsaid common packet, said common bus, said common packet switch, saidcommon packet platform, said external network protocol converter, andsaid internal network protocol converter are integrated on a chip sothat they can work as a single chip.
 16. The system of claim 9, whereinin order to support a plug and play function said common packet, saidcommon bus, said common packet switch, said common packet platform, saidexternal network protocol converter, and said internal network protocolconverter are designed as an open architecture, and external networks orinternal networks interwork with said common packet platform.